The present invention relates to a video decoder design, and more particularly, to a residual processing circuit using a single-path pipeline or a multi-path pipeline and an associated residual processing method.
The conventional video coding standards generally adopt a block based coding technique to exploit spatial and temporal redundancy. For example, the basic approach is to divide the whole source frame into a plurality of blocks, perform intra prediction/inter prediction on each block, transform residues of each block, and perform quantization and entropy encoding. Besides, a reconstructed frame is generated in a coding loop to provide reference pixel data used for coding following blocks. For certain video coding standards, in-loop filter(s) may be used for enhancing the image quality of the reconstructed frame.
A video decoder is used to perform an inverse operation of a video encoding operation performed by a video encoder. For example, regarding processing of residual data, transform, quantization, scan and entropy encoding are performed at the video encoder, while entropy decoding, inverse scan, inverse quantization, and inverse transform are performed at the video decoder. To improve the residual processing performance of the video decoder, pipeline architecture may be employed. Thus, there is a need for high performance pipeline architecture for dealing with inverse scan, inverse quantization, and inverse transform efficiently.